The present invention relates to a semiconductor apparatus including a conductive side wall on the side surfaces of a gate electrode and a production method for the semiconductor apparatus, and more particularly, it relates to a measure for attaining refinement and a high density in a semiconductor apparatus.
A MOS semiconductor apparatus having a so-called LDD structure as shown in FIG. 10 is well known. This semiconductor apparatus comprises, in an active area surrounded by an isolation 108 formed on a semiconductor substrate 101, a gate oxide film 102, a gate electrode 103, insulating side walls 107 formed on side surfaces of the gate electrode 104, low concentration source/drain regions 105a and 105b formed in the semiconductor substrate 101 under the side walls 107, high concentration source/drain regions 109a and 109b formed on the outer sides of and adjacently to the low concentration source/drain regions 105a and 105b, first and second contact holes 111a and 111b formed through an interlayer insulating film 110 so as to respectively reach the high concentration source/drain regions 109a and 109b, and first and second interconnections 112a and 112b formed within the contact holes 111a and 111b and on the interlayer insulating film 110. The MOS semiconductor apparatus having such an LDD structure has an advantage that degradation due to a punch-through and a hot carrier can be suppressed even when a gate length is shortened, and is known to be advantageous for refinement. In spite of such a merit, the MOS semiconductor apparatus having the LDD structure as shown in FIG. 10 has an inherent disadvantage that a hot carrier is captured by the side wall 107 so as to deplete the surfaces of the low concentration source/drain regions 105a and 105b, resulting in degrading the characteristics of the transistor.
As a countermeasure against this disadvantage, a side wall of a conductive material is used to suppress the degradation due to a hot carrier as is described in, for example, Japanese Laid-Open Patent Publication No. 2-276251. The production method for a MOS semiconductor apparatus disclosed in this publication will now be described. FIGS. 11(a) through 11(c), 12(a) through 12(c) and 13(a) through 13(c) are plane views showing the production procedures, sectional views in an active area and sectional views in an isolation.
First, as is shown in FIGS. 11(a) through 11(c), an isolation 122 is formed on a semiconductor substrate 121 so as to surround an active area. On the active area in the semiconductor substrate 121 is formed a MOS transistor including a gate oxide film 123, a gate electrode 124 of polysilicon, an insulating film 125, side walls 126 of polysilicon, a source region 127 and a drain region 128 doped with an impurity at a high concentration. In this exemplified transistor, no low concentration source/drain region is formed below the side wall 126.
Then, as is shown in FIGS. 12(a) through 12(c), a polysilicon film is deposited and selectively etched, thereby forming a connection layer 129 stretching over the insulating film 125 on the isolation 122 so as to connect the side walls 126. On the active area, however, the connection layer 129 remains not on the source region 127 but on the drain region 128.
Next, as is shown in FIGS. 13(a) through 13(c), an interlayer insulating film 132 is deposited on the entire surface of the resultant substrate, and then a contact hole 133 is formed through the interlayer insulating film 132 so as to reach the connection layer 129 on the drain region 128. Furthermore, an Al interconnection 130 is formed within the contact hole 133 and on the interlayer insulating film 132.
In the MOS transistor disclosed in this publication, the side wall 126 is made of a conductive material, and the drain region 128 and the side wall 126 are connected via the connection layer 129. Therefore, the side wall 126 is retained at the same potential as the drain region 128. Thus, an electric field in the vicinity of the drain region 128 in the semiconductor substrate is relaxed, thereby suppressing the degradation due to a hot carrier.
However, there have recently been more and more demands for refinement and a higher density of a MOS semiconductor apparatus, and the aforementioned structure of the MOS semiconductor apparatus cannot meet the demands.
For example, in the MOS semiconductor apparatus shown in FIG. 10, when a designing rule of 0.25 .mu.m or less is adopted, the gate length can be minimized to 0.25 .mu.m or less but the widths of the source/drain regions 107a and 107b cannot be sufficiently minimized because it is necessary to provide a margin (hereinafter referred to as the alignment margin) in consideration of a shift between a mask for forming a gate electrode and a mask for forming a contact hole.
On the other hand, in the structure disclosed in the aforementioned publication, the connection layer 129 is required to have a larger size than the contact hole 133 as is shown in FIG. 13(b). In addition, this structure requires not only the alignment margin between the gate electrode and the contact hole but also another alignment margin between the connection layer and the gate electrode. Therefore, the area occupied by the drain region 128 is further larger than that of the transistor having the LDD structure shown in FIG. 10. This can result in a reverse movement to the demands for refinement and a higher density.